Abstract
A low-complexity high performance Rayleigh fading simulator, and its Field Programmable Gate Array (FPGA) implementation are presented. This proposed method is a variant of the method of filtering of the white Gaussian noise where the filter design is accomplished in the analog domain and transferred into digital domain. The proposed model is compared with improved Jakes’ model, auto-regressive (AR) filtering, existing auto-regressive moving-average (ARMA) filtering techniques, and inverse discrete Fourier transform (IDFT)-based techniques, in performance and computational complexity. The proposed method outperforms AR(20) filter and modified Jakes’ generators in performance. Although IDFT method achieves the best performance, it brings a significant cost in storage. The proposed method achieves high performance with the lowest complexity, and its performance has been verified on commercially available FPGA platforms. Our fixed-point Rayleigh fading-channel emulator uses only 2% of the configurable slices, 1% of the Look-Up-Table (LUT) resources and 3% of the dedicated multipliers on the FPGA platform that has been used.
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Özen, S., Arsal, A. & Toker, K.A. Hardware realization of a low-complexity fading filter for multipath Rayleigh fading simulator. Electr Eng 93, 83–90 (2011). https://doi.org/10.1007/s00202-010-0190-2
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DOI: https://doi.org/10.1007/s00202-010-0190-2